1. Field of the Invention
The invention relates to circuits used with clocking signals, especially those designed to divide the clocking signal and to synchronize the divided signal with an external event.
2. Description of the Prior Art
In many electronic circuits, particularly those utilizing digital electronics and computers, it is necessary to produce clock signals having a number of different frequencies. It is generally desirable to use the lowest frequency master clock signal possible so that lower cost and lower performance processes can be used. To this end, it is often desirable that a master clock signal be divided by an odd integral value to produce one of the lower rate clock signals used elsewhere in the system or device.
In the past, one problem has been that conventional circuits which perform an odd division do not result in an output clock signal having a 50% duty cycle but rather generally have an n: n+1 duty cycle, where 2n+1 is the divisor value. If a 50% duty cycle divided clock signal was necessary, the master clock signal frequency had to be doubled so that there was an even division. This double rate master clock signal required the use of higher performance and higher cost processes throughout the circuits and the device.
An alternative to an integral division was the asynchronous generation of the lower rate clock signal. This was generally done using a separate crystal and associated circuitry to develop the clock signal. This need for additional components increased the expense of the device as compared to a simple division circuit and resulted in asynchronous clock signals If there was a necessity for synchronizing the various clock signals appearing in the device, the asynchronous generation required separate, generally complex, synchronizing circuitry. Generally the synchronizing circuitry would require the insertion of a large number of wait states or delays into one or both of the clock signals to synchronize the two clock signals. This insertion of numerous wait states resulted in long delays and therefore degradation of the performance of the device. The situation was further complicated if the clock signal had to be synchronized to any one of a plurality of master clocking signals so that the clock signal being synchronized would have to be delayed or held for a variable number of counts or cycles depending upon the frequency of the master clock signal.
It is therefore desirable to have a circuit which allows an odd valued division of a clock signal and yet produces a 50% duty cycle output and additionally allows easy synchronization of a divided clock signal with one of a plurality of master clock signals.